Structure for use in fabrication of pin heterojunction tfet

ABSTRACT

A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.12/684,331, filed on Jan. 8, 2010, the entire contents of which areincorporated herein by reference.

BACKGROUND

This disclosure relates generally to the field of semiconductor devicefabrication.

Tunnel field effect transistors (TFETs) offer improved sub-thresholdslope over other complementary metal-oxide-semiconductor (CMOS) devices.A TFET comprises a tunnel barrier, which may comprise a PiN junction. APiN junction is a semiconductor device having three contiguous regions:p-type doped, intrinsic, and n-type doped. The height of the tunnelbarrier may be modulated by the TFET gate potential, controlling thetransport current of the TFET. This mechanism of TFET transport currentcontrol may give a relatively steep sub-threshold slope. However, theability of the gate potential of a TFET to modulate the TFET tunnelbarrier height may lessen over time, as an inversion layer may form inthe TFET due to screening.

BRIEF SUMMARY

In one aspect, a structure for use in fabrication of a PiNheterojunction tunnel field effect transistor (TFET) includes a siliconwafer, the silicon wafer comprising an alignment trench and a p-typesilicon germanium (SiGe) region, wherein the silicon wafer furthercomprises a hydrogen implantation region in the silicon wafer underneaththe p-type SiGe region and the alignment trench, the hydrogenimplantation region dividing the silicon wafer into a upper siliconregion and a lower silicon region, and wherein the upper silicon regioncomprises the alignment trench and the p-type SiGe region; and a firstoxide layer located over the alignment trench and the p-type SiGe regionin the silicon wafer, wherein the oxide layer fills the alignmenttrench, and wherein the first oxide layer is bonded to a second oxidelayer located on a handle wafer, wherein the first oxide layer and thesecond oxide layer comprise a bonded oxide layer; wherein the alignmenttrench is configured to align a wiring level of the device comprisingthe PiN heterojunction TFET to the p-type SiGe region during formationof the device comprising the PiN heterojunction TFET.

Additional features are realized through the techniques of the presentexemplary embodiment. Other embodiments are described in detail hereinand are considered a part of what is claimed. For a better understandingof the features of the exemplary embodiment, refer to the descriptionand to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alikein the several FIGURES:

FIG. 1 illustrates an embodiment of a method for fabricating a structurefor use in fabricating a PiN heterojunction TFET.

FIG. 2 illustrates an embodiment of a wafer comprising an alignmentlayer.

FIG. 3 illustrates an embodiment of a wafer after application of a hardmask layer.

FIG. 4 illustrates an embodiment of a wafer after application of resist.

FIG. 5 illustrates an embodiment of a wafer after patterning of the hardmask layer and removal of the resist.

FIG. 6 illustrates an embodiment of a wafer after etching of a silicongermanium growth trench.

FIG. 7 illustrates an embodiment of a wafer after growth of p-type dopedsilicon germanium in the silicon germanium growth trench.

FIG. 8 illustrates an embodiment of a wafer after removal of the hardmask.

FIG. 9 illustrates an embodiment of a wafer after polishing.

FIG. 10 illustrates an embodiment of a wafer after formation of an oxidelayer.

FIG. 11 illustrates an embodiment of a wafer after hydrogenimplantation.

FIG. 12 illustrates an embodiment of a handle wafer.

FIG. 13 illustrates an embodiment of a wafer after bonding to the handlewafer.

FIG. 14 illustrates an embodiment a structure for use in fabrication ofa PiN heterojunction TFET.

DETAILED DESCRIPTION

Embodiments of systems and methods for fabricating a structure for usein fabrication of a TFET having a tunnel barrier comprising a PiNheterojunction are provided, with exemplary embodiments being discussedbelow in detail. In a PiN heterojunction, at least one of the threeregions comprising the heterojunction is made from a different materialfrom the other regions. A PiN heterojunction TFET may operate at itsquantum capacitance limit, at which the total gate capacitance isdominated by the semiconductor, or quantum, capacitance as opposed tothe geometrical oxide capacitance. At the quantum capacitance limit,substantial scaling benefits are obtained. Screening is reduced, and theTFET gate potential may have relatively strong control of the tunnelbarrier height. Control of the tunnel barrier height may be independentof the applied gate bias. A linear change in the TFET gate bias maycause a linear change in the tunnel barrier height, and an exponentialchange in the TFET transport current. The structure also comprises azero level trench, or alignment trench, for aligning additional wiringlayers that may be formed in subsequent processing steps.

FIG. 1 illustrates an embodiment of a method 100 for fabricating astructure for use in fabrication of a PiN heterojunction TFET. FIG. 1 isdiscussed with reference to FIGS. 2-14. In block 101, a zero leveltrench, or alignment trench, and a SiGe growth trench are formed in asilicon wafer. The zero level trench acts as an alignment layer that maybe used to align wiring levels in that are formed in subsequentprocessing steps, including the gate polysilicon conductor layer (PC)and active silicon conductor layer (RX). One embodiment of a method offorming a zero level trench and a SiGe growth trench is shown in FIGS.2-6. First, as shown in FIG. 2, a zero level trench 202 is formed insilicon 201. Zero level trench 202 may be formed using either silicondioxide or silicon nitride in some embodiments. As shown in FIG. 3, ahard mask 301 is then formed on silicon 201. Mask 301 may comprise anoxide or a nitride in some embodiments. Then, as shown in FIG. 4,photoresist 401 is deposited on hard mask 301. The hard mask 301 is thenpatterned and photoresist 401 is removed as shown in FIG. 5, resultingin etched mask regions 501 on silicon 201. Then as shown in FIG. 6,silicon germanium (SiGe) growth trench 601 is etched in silicon 201. Thedepth of SiGe growth trench 601 may be on the order of about 50nanometers (nm). In another embodiment, mask 301 and photoresist 401 maybe deposited on silicon 401 before zero level trench 202 is formed, insuch a manner that zero level trench 202 may be formed in silicon 201simultaneously with the etching of trench 601.

In block 102, as shown in FIG. 7, in-situ P-type doped SiGe 701 is grownin SiGe growth trench 601. P-doped SiGe 701 may be doped with boron insome embodiments. The depth of SiGe 701 may be on the order of about 50nm in some embodiments.

In block 103, as shown in FIG. 8, etched mask 501 is removed, leavingzero level trench 202 in silicon 201. Polishing may then be performed asshown in FIG. 9, resulting in polished SiGe 901. The polishing maycomprise chemical mechanical polishing (CMP) in some embodiments; anyappropriate polishing method may be used to planarize silicon 201 andSiGe 901. Then, as shown in FIG. 10, a dielectric layer comprising anoxide layer 1001 is formed on the surface of silicon 201 and SiGe 901,and in zero level trench 202. Oxide layer 1001 may be formed by anyappropriate method including but not limited to atomic layer deposition(ALD) or chemical vapor deposition (CVD). Oxide layer 1001 may beplanarized by any appropriate method after it is formed.

In block 104, as shown in FIG. 11, high-energy hydrogen is implantedinto silicon 201 to form hydrogen implantation region 1101. Implantationregion 1101 forms a cleaving plane between upper silicon region 1103 andlower silicon region 1102.

In block 105, wafer 1200 is bonded to a handle wafer comprising bulksilicon 1201 and a top thermal oxide 1202, as shown in FIG. 12. Topthermal oxide 1202 bonds with oxide layer 1001, as shown in FIG. 13,resulting in oxide layer 1301. Oxide layer 1301 may be between about 50to about 400 nm thick in some embodiments.

In block 106, wafer 1300 is annealed, releasing silicon 1102 fromsilicon 1103 at the cleaving plane comprising implantation region 1101.Annealing may comprise spike annealing or flash annealing. The resultingstructure 1400, shown in FIG. 14, may then be polished, resulting in athickness of silicon 1103 between about 10 to about 50 nm in someembodiments. Polishing may comprise CMP in some embodiments.

Structure 1400 comprises a top-down silicon nanowire structure for usein fabrication of a PiN heterojunction TFET device. P-type SiGe region901 comprises a nanowire, and may comprise the p-type region of a PiNheterojunction that may comprise a TFET tunnel barrier. Structure 1400also comprises an alignment layer (i.e., zero level trench 202) that maybe used to align wiring levels that are formed in subsequent fabricationsteps, including the gate polysilicon conductor layer (PC) and activesilicon conductor layer (RX), to the p-type SiGe nanowire layer. A PiNheterojunction may be formed on structure 1400 using top-down nanowirefabrication methods. The n-type region of the PiN heterojunction may beformed by n-type diffusion implant, which may be performed using eithernon-self aligned masking (as in lateral TFET devices) or through a highangle asymmetric implantation. The n-doped portion of the PiNheterojunction structure may comprise self-aligned doped n-typematerial.

The technical effects and benefits of exemplary embodiments includefabrication of a PiN heterojunction TFET that may operate at its quantumcapacitance limit.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A structure for use in fabrication of a PiN heterojunction tunnelfield effect transistor (TFET), the structure comprising: a siliconwafer, the silicon wafer comprising an alignment trench and a p-typesilicon germanium (SiGe) region, wherein the silicon wafer furthercomprises a hydrogen implantation region in the silicon wafer underneaththe p-type SiGe region and the alignment trench, the hydrogenimplantation region dividing the silicon wafer into a upper siliconregion and a lower silicon region, and wherein the upper silicon regioncomprises the alignment trench and the p-type SiGe region; and a firstoxide layer located over the alignment trench and the p-type SiGe regionin the silicon wafer, wherein the oxide layer fills the alignmenttrench, and wherein the first oxide layer is bonded to a second oxidelayer located on a handle wafer, wherein the first oxide layer and thesecond oxide layer comprise a bonded oxide layer; wherein the alignmenttrench is configured to align a wiring level of the device comprisingthe PiN heterojunction TFET to the p-type SiGe region during formationof the device comprising the PiN heterojunction TFET.
 2. The structureof claim 1, wherein the p-type SiGe region comprises in-situ boron-dopedSiGe, and wherein the depth of the p-type SiGe region is about 50 nm orless.
 3. The structure of claim 1, wherein the thickness of the siliconlayer is between about 10 nm and about 50 nm.
 4. The structure of claim1, wherein the thickness of the oxide layer is between about 50 nm andabout 400 nm.
 5. The structure of claim 1, further comprising a PiNheterojunction that comprises a p-type region, the p-type regioncomprising the p-type SiGe region.
 6. The structure of claim 5, furthercomprising a TFET, the TFET comprising a tunnel barrier, the tunnelbarrier comprising the PiN heterojunction.
 7. The structure of claim 1,wherein the handle wafer comprises the second oxide layer and a bulksilicon layer.
 8. The structure of claim 1, wherein the thickness of thebonded oxide layer is between about 50 nm and about 400 nm